Prof. Tsuneo Nakanishi (Fukuoka University)
Software Product Lines and Its Practical Application in Industry-Academia Collaboration
Abstract: Software product lines (or SPLs) is a software development paradigm to develop multiple product variants with commonality and variability by reusing shared core assets with a prescribed process. It has a history of more than two decades and many companies has circumstance that they should introduce SPLs; however, conservative companies has tended to hesitate its introduction so far.
The talk consists of two parts.
In the first part, fundamental ideas of the SPL paradigm is introduced for audience who are not familiar with the paradigm. They may seem textbook-like, abstract, or conceptual; and that will be exactly a reason why engineers in the industry often misrecognize this paradigm as “academic” ideas.
In the second part, based on experiences in industry-academic collaboration with some companies, the speaker discloses know-hows and pitfalls to introduce SPLs into real development projects. The way of introduction depends on conditions of products and culture of the company. There does not exist a universal process for introduction. “Know the products and culture and write a prescription of introduction with keeping SPL’s paradigm in mind” — that is the speaker’s key message.
Biography: Tsuneo Nakanishi received Ph. D from Nara Institute of Science and Technology, Japan, in 1998. He works for Fukuoka University as a professor in the Department of Electronics Engineering and Computer Science. His research interests include software engineering for embedded/automotive systems. He has evangelized software product line engineering to industries and succeeded in its introduction to real projects in some companies.
Prof. Hiroki Nakahara (Tokyo Institute of Technology)
Deep Learning Accelerators on an FPGA
Abstract: With the development of deep learning, the market for an edge AI including embedded systems is expected to expand in the market point of view. Edge AIs need to process a large number of operations on limited computational and power resources. Data structures and architectures have been researched and developed.
Previous studies have proposed networks as various data structures. We introduce various networks that are effective for hardware implementation. Next, we describe a weight reduction method for hardware implementation. It is a quantization in low bits. High speed can be achieved while reducing the amount of dedicated hardware by quantization techniques. However, the recognition accuracy deteriorates, so we consider the optimization method. Next, we show a weight sparseness that approximates the weight to 0. It also exits a trade-off with accuracy deterioration and acceleration, so we introduce the optimization method.
Finally, we describe three types of hardware implementations. The implementation results will be demonstrated targeting an FPGA as a prototype of deep learning applications.
Biography: Hiroki Nakahara received the B.E., M.E., and Ph.D. degrees in computer science from Kyushu Institute of Technology, Fukuoka, Japan, in 2003, 2005, and 2007, respectively. He has held research/faculty positions at Kyushu Institute of Technology, Iizuka, Japan, Kagoshima University, Kagoshima, Japan, and Ehime University, Ehime, Japan. Now, he is an associate professor at Tokyo Institute of Technology, Japan and CEO/CRO/Co-Founder at Tokyo Artisan Intelligence Co., Ltd.
He was the Workshop Chairman for the International Workshop on Post-Binary
ULSI Systems (ULSIWS) in 2014, 2015, 2016 and 2017, respectively. He served the Program Chairman for the International Symposium on 8th Highly-Efficient Accelerators and Reconfigurable Technologies (HEART) in 2017. He received the 8th IEEE/ACM MEMOCODE Design Contest 1st Place Award in 2010, the SASIMI Outstanding Paper Award in 2010, IPSJ Yamashita SIG Research Award in 2011, the 11st FIT Funai Best Paper Award in 2012, the 7th IEEE MCSoC-13 Best Paper Award in 2013, and the ISMVL2013 Kenneth C. Smith Early Career Award in 2014, respectively. His research interests include logic synthesis, reconfigurable architecture, digital signal processing, embedded systems, and machine learning. He is a member of the IEEE, the ACM, and the IEICE.
He is a member of the IEEE, the ACM, and the IEICE.